1. Field of the Invention
The present invention relates to a method and system for performing automated placing and routing (P&R). More specifically, the present invention relates to a set of rules for improving the process of conducting automated place and route.
2. Related Art
In the related art System On a Chip (SOC), and for other big chips built in very large scale integration (VLSI), cost and time to market are very important criteria for determining effectiveness. The related art SOC have become bigger, and may include tens of millions of transistors that result in very complex floor planning, with many sub blocks in a hierarchy. Accordingly, a different approach is needed for the layout implementation for the larger related art SOC, as compared with a completely flat layout of relatively small related art VLSI chips.
Related art place and route (P&R) automated tools give a complete and relatively good solution for sub micron technology chip layout, if the chip layout can be done by one flat netlist. However, in SOC, the efficiency of the P&R tools is very poor if they are used for millions of cells as one hierarchy. As a result, it is desirable to implement such chips with relatively few sub blocks, each sub-block being built completely by the P&R tool, rather than combining all of the sub-blocks together in the Top Level of the chip, either by the P&R tool or manually, to build the complete chip.
However, the foregoing related art layout scheme has various problems and disadvantages. For example, but not by way of limitation, a substantial amount of layout work is needed to build the chip layout in hierarchy or by sub blocks, and significant human resources are required. Many related art layout methodologies can do this work, each tool depending on the specific layout requirements. There are also common related art layout methodologies related to the chip that are designed from block “type”. Those related art approaches result in a relatively long work process, until the related art SOC layout is completed. These related art approaches depend on at least chip size, speed of operation, complexity of the integration and amount of routing and power consumption.
In a related art layout methodology, a VLSI chip is built by sub block, and not as a flattened chip. As a result, there are at least the following disadvantageous bottlenecks. First, each sub block is designed as a separated stand-alone unit, which results in overhead. Further, each block power strip line needs to be designed in a customized way to improve efficiency. For example, but not by way of limitation, in each block that contains a memory, additional resources must be devoted to the issue of how to integrate this memory cell. As a result, a non-optimum layout of resources is produced (e.g., in terms of area, pins location and routing resources).
Additionally, there is a related art problem when combining all sub blocks together, which results in a layout penalty due to the blocks. For example, but not by way of limitation, there is a different aspect ratio, surrounding of power and ground metals, rings and pins location inside the power rings. Also, input/output (IO's) and IP cell integration usually require a relatively long time.
With related art method and P&R tools, a team of 8 Engineers will need to work for 6 months to complete the layout of the VLSI chip, which is a disadvantage of the related art.